This invention relates to semiconductor memories; and more particularly to that portion of the memory which operate to restore charge into the memory cells during a read operation. The most common architecture for semiconductor memories of the type with which we are concerned with here includes an array of memory cells, and a plurality of sense amplifiers selectively coupled to those cells via bit lines. The amplifiers sense charge in the cells during the read operation.
Each sense amplifier includes a pair of cross-coupled transistors having gates coupled to respective bit lines. Initially, the bit lines are precharged to a predetermined voltage level. Subsequently, one of the memory cells is selectively gated onto one of the bit lines, and a dummy cell (which has substantially less storage capacity than the memory cells) is gated onto the other bit line. As a result, the precharge voltage levels are modified slightly to indicate the data that was stored in the selected memory cell.
Next the source of the two cross-coupled transistors in the sense amplifier are connected to ground. In response thereto, the modified voltage levels of the bit lines begin to discharge towards ground at respective rates which indicate the data that was stored in the selected memory cell. That data is represented as either a relatively high voltage level or a relatively low voltage level. In the case where the selected cell contained a relatively high voltage level, that level is lowered somewhat; and it must be fully restored into the memory cell. That function is performed by the presently disclosed charge restore circuits.
Several other charge restore circuits also exist in the prior art. However, those circuits all exhibit various undersirable characteristics. For example, it is important that the charge restore circuit contains as few components as possible. This is because in a semiconductor memory, chip space is at a premium. Thus a recharge circuit is of no practical value unless it can be efficiently laid out in accordance with the array of memory cells.
Further, it is important that the charge restore circuit be operable over a wide range of precharge voltage levels for the bit lines. This provides an operating margin for the memory. That is, it enables the memory to function properly even though the supply voltages are not held within a tight tolerance.
In addition, it is desirable that the charge restore circuits dissipate as little power as possible. This is because power dissipation produces heating; and that in turn requires a means be provided for dissipating the heat from the memory chip. Otherwise, the operating temperature limits of the memory chip will be exceeded.
None of the prior art charge restore circuits for semiconductor memories offer all of the above features. Further discussion of this point is included herein in conjunction with the description of FIGS. 5 and 6. Therefore, it is a primary object of the invention to provide an improved charge restore circuit for semiconductor memories wherein all of the above features are achieved.